1. Field of the Invention
The present invention relates generally to row and column drivers of a display panel. More particularly, the present invention relates to a method and apparatus for compensating propagation delay in display drivers through delaying a column driver enable signal by a time approximating the delay experienced by signals propagating in a corresponding row signal line. The present invention also relates to a method and apparatus for compensating propagation delay in display drivers through delaying a row driver enable signal by a time approximating the delay experienced by signals propagating in a corresponding column signal line.
2. Description of the Relevant Art
Many display panels, such as those used as televisions, computer monitors, and other video and stationary image displays, include a lattice of display signal lines formed in a plurality of rows and columns. Each junction of the lattice includes a switching device, typically a thin film transistor (TFT), a storage device, such as a capacitor, and an associated display element or pixel. To activate the switching devices to store the voltages necessary for appropriate pixels to display an image, column and row drivers are used in conjunction with one or more display controllers. The display controllers generate timing signals, such as column and row driver enable signals, for the respective column and row drivers which, in turn, generate appropriate voltage signals for specific pixel addresses. The use of pixels arranged in a lattice, as opposed to a cathode ray tube, enables relatively large display areas with relatively small display panel thickness.
The construction of a liquid crystal display (LCD) panel, for example, includes a plurality of addressed pixels formed in a lattice of pixel rows and columns. Each pixel in the lattice is addressed by a row selection signal line and a column driver signal line; a desired driving voltage is applied to such pixel, via the column driver signal line, when its row is selected via the row selection signal line. The aforementioned row selection signal line and column driver signal line are each coupled to control circuitry that determines what voltage will be applied to each pixel in a common row when that row is selected. In a color display panel, each position in the lattice preferably includes three subpixels for respectively emitting the primary colors red, green, and blue to provide a full color display panel. During pixel addressing periods, individual row signal lines are selectively enabled to select one row of pixels at a time, and column signal lines of the LCD panel are selectively driven with voltages unique to the current image content of the LCD panel. Selective address voltages are generated by driver controllers that are specifically designed for direct coupling to the LCD panel row and column signal lines.
To refresh a display panel, a row enable signal is transmitted to a first row of display pixels. This row enable signal activates the transistors associated with each of the pixels on that row and enables the transistors to transfer voltages on the column signal lines to the capacitors associated with the relevant pixels in that row. Substantially simultaneous with the row enable signal activation, a select plurality of the column signal lines is activated and voltages are transferred to the appropriate capacitors. For color displays, each pixel is associated with three column signal lines (red, green and blue). The column signal line through which the voltage is transferred and the magnitude of that voltage determines what color an associated pixel will be, and with what intensity the color will display. After a predetermined time for transfer, the row enable signal is switched low, storing the transferred voltage value in the capacitor. After a delay, the process is then repeated for the next sequential row on the display panel until all rows have been refreshed.
Early display panels were manufactured to have a screen size on the order of 10″ (diagonal measurement) with a pixel density of 640×480 pixels, and delay problems resulting from a signal traveling from circuitry at one end of the display to the circuitry at another end of the display were considered by many to be negligible. Over time, however, display panels have become larger and pixel density has increased. These changes in display panels have compounded the once minor delay problems to a point that they should no longer be considered negligible.
As an illustration of the significance of potential delay involved in a refresh cycle, a conventional QXGA display having 2,048 vertical columns and 1,536 horizontal rows of pixels will be discussed. For each vertical column of pixels in a color display, there are actually three vertical columns of storage devices for storing values, one each for red, green and blue. Therefore, in a color QXGA display, there are 6,146 columns and 1,536 rows of signal lines. Displays are conventionally completely refreshed at a rate of at least 60 times per second, or at 60 Hz, to avoid flicker. Other displays, for example QSXGA+ displays, have even higher densities of pixels. With a QXGA color display having 1,536 rows of signal lines, the maximum time available to refresh each row (tRmax) is:       t          R      ⁢                           ⁢      max        =                    (                  1                      60            ⁢                                                   ⁢            s                          )                    1536        ⁢                                   ⁢        rows              =          10.85      ⁢                           ⁢      µs      ⁢              /            ⁢      row      For each additional row of pixels added to the display, the available time to refresh those pixels decreases. Furthermore, at points where display row and column signal lines cross, parasitic capacitance is observed between the conductive signal lines. This parasitic capacitance may further slow signal propagation. Conventionally, there is approximately a 1 to 2.5 microseconds delay in the row enable signal by the end of a signal line in a QXGA display. In other words, if the row enable signal applied at one end of the row enable line switches from low to high at time zero, then the low to high transition will not appear at the opposite end of the row enable line in anywhere from 1 to 2.5 microseconds later. Increasingly greater effort must be spent in the design of larger format display panels in order to maintain such propagation delays within reasonably small values. Practical factors currently limiting the state of the art dictate that such propagation delay be approximately 1 to 2.5 microseconds. Despite there only being approximately one-quarter the number of pixels in an XGA display as in a QXGA display, the row enable signal propagation delay of an XGA display is approximately the same as that observed in a QXGA display. As discussed in greater detail hereinafter, display signal propagation delay may cause noticeable uneven display intensity or even display errors.
In attempts to resolve what has previously been considered only a minor problem, others have used wider, less resistive, signal lines to increase signal propagation and decrease delay. However, as the physical dimensions of the signal lines are increased, the physical space available for use as pixels necessarily decreases; this results in decreased pixel size, or aperture, and hence, less display surface area for active light modulation. In turn, less active light modulation area results in more light source power for the same display brightness effect. Increasing the thickness of the address conductors reduces the resistance at the expense of fabrication time. Reducing the overlap capacitance between the row and column line conductors through thicker dielectric separation also results in added fabrication expense. Other attempts at resolving the effects of display signal propagation delay include providing duplicate column drivers, one at the top of the display and one at the bottom of the display, and duplicate row drivers, one at the left of the display and one at the right of the display. Displays using these approaches, however, require additional circuitry and still may experience the varied pixel intensity problems caused by signal propagation delay.